1. Field of the Invention
The present invention relates to latches and flip-flops, and more particularly to CMOS circuit designs of latches and flip-flops.
2. State of the Art
Latches and flip-flops are well known basic building blocks in synchronous logic circuit designs. In general, latches and flip-flops function as memory elements in that output voltage levels depend upon past as well as present voltage levels. The operation of sequential logic gates is such that when new inputs are applied, the outputs respond according to the new inputs and the previous inputs. Upon removal of the inputs, the outputs then remain unchanged. In particular, a latch can change output states continuously corresponding to input changes in any instant, whereas a flip-flop changes outputs states at instants controlled by a clock signal.
In general, flip-flops are formed by cascading two consecutive latch stages together (referred to as master and slave latches) that are clocked (i.e., enabled) at different times. FIG. 1 shows a typical implementation of a flip-flop having a master latch and a slave latch consecutively coupled and clocked such that the master latch and the slave latch are enabled at opposite clock phases.
Clock signals function to enable (or disable) the latches and flip-flops dependent on the voltage level or transition type (i.e., HIGH-to-LOW or LOW-to-HIGH) of the clock signal. Latches and flip-flops can be clocked in a variety of different manners requiring a varying number of clock signals. Some latch and flip-flop clocking techniques are described in an article entitled "High-Speed CMOS Circuit Technique" by Jiren Yuan and Christer Svensson (IEEE Journal of Solid State Circuits, Vol 24, No. 1, February 1989) and in an article entitled "New Single-Clock CMOS Latches and Flip-Flops with Improved Speed and Power Savings" by Jiren Yuan and Christer Svensson (IEEE Journal of Solid State Circuits, Vol 32, No. 1, January 1997).
In the sequential logic design shown in FIG. 2A including logic blocks 1 and 2 and latching stages L1 and L2, a clocked CMOS logic (i.e., C.sup.2 MOS) technique is used. In this technique, two non-overlapping clock signals, .phi..sub.1 and .phi..sub.2, and their complements, .phi..sub.1 / and .phi..sub.2 /, (FIG. 2B) are used to clock latching stages L1 and L2. In this case, effectively four phases are used to clock the logic design.
In a second technique referred to as NORA dynamic CMOS technique, two phases, .phi. and .phi./, of a single clock signal is used (FIGS. 3A and 3B). In this case, latching stage L3 is clocked with the .phi. clock signal and latching stage L4 is clocked with the .phi./ clock signal. Latching stage L3 and L4 can be alternated within the logic design for sequential signal propagation such as shown in FIG. 2A.
The disadvantage of both of the above described techniques is that signal skews can develop when more than one clock is used and when a clock and its complement is used. In addition, these designs require additional logic elements to obtain inverted clock signals. The true single-phase clock (TSPC) dynamic CMOS circuit technique overcomes these disadvantages by using a single clock phase to clock latch stages. The latch stages are referred to as block or P-block depending on whether the clock is applied to an n or p type device. FIG. 4 shows an example of an N-block TSPC latch coupled to a P-block TSPC latch to form a flip-flop requiring a single clock signal .phi.. This logic gate has a single ended input IN and provides non-inverted and inverted signals (D and D/) using inverter INV. In this case the two output signals are referred to as a pseudo differential output signal since the two signals are generated by inverting a single-ended output of the flip-flop instead of having two distinct output ports for providing a true differential signal. The advantage of having a differential output signal is that other logic blocks often require a signal and its complement to perform the desired logic function. Furthermore, using an inverter to provide pseudo differential outputs can introduce signal skews between input signals to subsequent stages unlike true differential signals.
Hence, in addition to clocking techniques, another important design aspect of latches and flip-flops is whether they are designed to provide a single-ended output (i.e., a single non-inverted output signal) or a differential output (i.e., a non-inverted output signal and its inverted complement). FIGS. 5A and 5B show differential input/output true single phase latches in which either a p-type device (FIG. 5A) or an n-type device (FIG. 5B) is used for clocking the latch. FIG. 5C shows a true single phase flip-flop implemented using the latches shown in FIGS. 5A and 5B.
As shown in FIG. 2A, synchronous logic is often implemented by alternating logic circuit stages which perform logic functions (e.g. Boolean logic) with logic circuit stages that perform latch (or flip-flop) functions. Hence, logic functions and latch or flip-flop functions are always performed by separate logic circuits which are alternately clocked. In this type of system it is often necessary to adapt differential and/or single-ended inputs and outputs when coupling the logic and latch stages to match previous and subsequent stage inputs. For instance, a latch stage may provide a single-ended output which needs to be converted to a differential output for the next stage. In addition, each separate stage takes a finite amount of time to perform its corresponding logic and latch (or flip-flop) function. Hence, the more stages used to implement the sequential logic, the longer it takes to process data through it. Consequently, although the true single phase clock logic technique has increased clocking speed, it still requires separate logic stages to be combined with the latching stages to implement a sequential logic circuit.